A typical SRAM memory is designed to store many thousands of bits of information. These bits are stored in individual memory cells that are organized into rows and columns to make efficient use of space on a semiconductor substrate in an integrated circuit. A basic storage element is the six transistor SRAM cell, which may be written into and read from under SRAM memory control. In SRAM arrays having interleaved words in a same row, some of the six transistor storage cells are subject to being upset when writing into fully selected cells. A read buffer may be added to the basic six transistor cell to provide read buffering of the cell, thereby reducing its tendency to upset. However, addition of these transistors increases the leakage current of the SRAM array. Improvements in this area would prove beneficial in the art.